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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM6209C/D
64K x 4 Bit Fast Static RAM
With Output Enable
The MCM6209C is fabricated using Motorola's high-performance silicon-gate CMOS technology. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for greater reliability. This device meets JEDEC standards for functionality and pinout, and is available in plastic dual-in-line and plastic small-outline J-leaded packages. Single 5 V 10% Power Supply Fully Static -- No Clock or Timing Strobes Necessary Fast Access Times: 12, 15, 20, 25, and 35 ns Equal Address and Chip Enable Access Times Output Enable (G) Feature for Increased System Flexibility and to Eliminate Bus Contention Problems * Low Power Operation: 135 - 165 mA Maximum AC * Fully TTL Compatible -- Three-State Output * * * * *
MCM6209C
P PACKAGE 300 MIL PLASTIC CASE 710B-01
J PACKAGE 300 MIL SOJ CASE 810B-03
PIN ASSIGNMENT
NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A15 A14 A13 A12 A11 A10 NC NC DQ0 DQ1 DQ2 DQ3 W
BLOCK DIAGRAM
A1 A2 A3 A4 A6 A12 A13 A14 ROW DECODER MEMORY ARRAY 256 ROWS x 64 x 4 COLUMNS VCC VSS
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 E G
DQ0 DQ1 DQ2 DQ3 INPUT DATA CONTROL
COLUMN I/O COLUMN DECODER
VSS
PIN NAMES
A0 A5 A7 A8 A9 A10 A11 A15 A0 - A15 . . . . . . . . . . . . . Address Input DQ0 - DQ3 . . . Data Input/Data Output W . . . . . . . . . . . . . . . . . . . . Write Enable G . . . . . . . . . . . . . . . . . . . Output Enable E . . . . . . . . . . . . . . . . . . . . . . Chip Enable NC . . . . . . . . . . . . . . . . . No Connection VCC . . . . . . . . . . . Power Supply (+ 5 V) VSS . . . . . . . . . . . . . . . . . . . . . . . Ground
E W G
REV 3 5/95
(c) Motorola, Inc. 1995 MOTOROLA FAST SRAM
MCM6209C 1
TRUTH TABLE (X = Don't Care)
E H L L L G X H L X W X H H L Mode Not Selected Output Disabled Read Write VCC Current ISB1, ISB2 ICCA ICCA ICCA Output High-Z High-Z Dout High-Z Cycle -- -- Read Write
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating Power Supply Voltage Voltage Relative to VSS For Any Pin Except VCC Output Current Power Dissipation Temperature Under Bias Operating Temperature Storage Temperature -- Plastic Symbol VCC Vin, Vout Iout PD Tbias TA Value - 0.5 to + 7.0 - 0.5 to VCC + 0.5 20 1.0 - 10 to + 85 0 to + 70 Unit V V mA W C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.
Tstg - 55 to + 125 C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 10%, TA = 0 to 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage Symbol VCC VIH VIL Min 4.5 2.2 - 0.5* Typ 5.0 -- -- Max 5.5 VCC + 0.3** 0.8 Unit V V V
* VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width 20 ns) ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width 20 ns)
DC CHARACTERISTICS
Parameter Input Leakage Current (All Inputs, Vin = 0 to VCC) Output Leakage Current (E = VIH or G = VIH, Vout = 0 to VCC) Standby Current (E VCC - 0.2 V*, Vin VSS + 0.2 V, or VCC - 0.2 V, VCC = Max, f = 0 MHz) Output Low Voltage (IOL = 8.0 mA) Output High Voltage (IOH = - 4.0 mA) Symbol Ilkg(I) Ilkg(O) ISB2 VOL Min -- -- -- -- Max 1 1 20 0.4 -- Unit A A mA V V
VOH 2.4 *For devices with multiple chip enables, E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E.
POWER SUPPLY CURRENTS
Parameter AC Supply Current (Iout = 0 mA, VCC = Max, f = fmax) Standby Current (E = VIH , VCC = Max, f = fmax) Symbol ICCA ISB1 - 12 165 55 - 15 155 50 - 20 145 45 - 25 135 40 - 35 130 35 Unit mA mA
MCM6209C 2
MOTOROLA FAST SRAM
CAPACITANCE (f = 1 MHz, dV = 3 V, TA = 25C, Periodically Sampled Rather Than 100% Tested)
Characteristic Address Input Capacitance Control Pin Input Capacitance (E, G, W) I/O Capacitance Symbol Cin Cin CI/O Max 6 6 8 Unit pF pF pF
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 10%, TA = 0 to + 70C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . Figure 1A Unless Otherwise Noted
READ CYCLE (See Notes 1 and 2)
- 12 Parameter Read Cycle Time Address Access Time Enable Access Time Output Enable Access Time Output Hold from Address Change Enable Low to Output Active Enable High to Output High-Z Output Enable Low to Output Active Output Enable High to Output High-Z Power Up Time Power Down Time Symbol tAVAV tAVQV tELQV tGLQV tAXQX tELQX tEHQZ tGLQX tGHQZ tELICCH tEHICCL Min 12 -- -- -- 4 4 0 0 0 0 -- Max -- 12 12 6 -- -- 6 -- 6 -- 12 - 15 Min 15 -- -- -- 4 4 0 0 0 0 -- Max -- 15 15 8 -- -- 8 -- 7 -- 15 - 20 Min 20 -- -- -- 4 4 0 0 0 0 -- Max -- 20 20 10 -- -- 9 -- 8 -- 20 - 25 Min 25 -- -- -- 4 4 0 0 0 0 -- Max -- 25 25 12 -- -- 10 -- 10 -- 25 - 35 Min 35 -- -- -- 4 4 0 0 0 0 -- Max -- 35 35 15 -- -- 10 -- -- -- 35 Unit ns ns ns ns ns ns ns ns ns ns ns 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 3 Notes 2
NOTES: 1. W is high for read cycle. 2. All timings are referenced from the last valid address to the first transitioning address. 3. Addresses valid prior to or coincident with E going low. 4. At any given voltage and temperature, tEHQZ max is less than tELQX min, and tGHQZ max is less than tGLQX min, both for a given device and from device to device. 5. Transition is measured 500 mV from steady-state voltage with load of Figure 1B. 6. This parameter is sampled and not 100% tested. 7. Device is continuously selected (E = VIL, G VIL).
AC TEST LOADS
+5V RL = 50 OUTPUT Z0 = 50 VL = 1.5 V OUTPUT 255 5 pF 480
TIMING LIMITS
The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.
Figure 1A
Figure 1B
MOTOROLA FAST SRAM
MCM6209C 3
READ CYCLE 1 (See Note 8)
tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID tAVQV DATA VALID
READ CYCLE 2 (See Notes 2 and 4)
tAVAV A (ADDRESS) tELQV E (CHIP ENABLE) tEHQZ tELQX G (OUTPUT ENABLE) tGLQV tGLQX Q (DATA OUT) HIGH-Z DATA VALID tAVQV VCC SUPPLY CURRENT ICC ISB tELICCH tEHICCL HIGH-Z tGHQZ
MCM6209C 4
MOTOROLA FAST SRAM
WRITE CYCLE 1 (W Controlled, See Notes 1, 2, and 3)
- 12 Parameter Write Cycle Time Address Setup Time Address Valid to End of Write Write Pulse Width Write Pulse Width, G High Data Valid to End of Write Data Hold Time Write Low to Output High-Z Write High to Output Active Symbol tAVAV tAVWL tAVWH tWLWH, tWLEH tWLWH, tWLEH tDVWH tWHDX tWLQZ tWHQX Min 12 0 10 10 8 6 0 0 4 Max -- -- -- -- -- -- -- 6 -- - 15 Min 15 0 12 12 10 7 0 0 4 Max -- -- -- -- -- -- -- 7 -- - 20 Min 20 0 15 15 12 8 0 0 4 Max -- -- -- -- -- -- -- 8 -- - 25 Min 25 0 20 20 15 10 0 0 4 Max -- -- -- -- -- -- -- 10 -- - 35 Min 35 0 20 20 15 10 0 0 4 Max -- -- -- -- -- -- -- 10 -- Unit ns ns ns ns ns ns ns ns ns 5, 6, 7 5, 6, 7 4 Notes 3
Write Recovery Time tWHAX 0 -- 0 -- 0 -- 0 -- 0 -- ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. For Output Enable devices, if G goes low coincident with or after W goes low, the output will remain in a high impedance state. 3. All timings are referenced from the last valid address to the first transitioning address. 4. For Output Enable devices, if G VIH, the output will remain in a high impedance state 5. At any given voltage and temperature, tWLQZ max is less than tWHQX min, both for a given device and from device to device. 6. Transition is measured 500 mV from steady-state voltage with load of Figure 1B. 7. This parameter is sampled and not 100% tested.
WRITE CYCLE 1 (W Controlled, See Note 2)
tAVAV A (ADDRESS) tAVWH E (CHIP ENABLE) tWLWH tWLEH W (WRITE ENABLE) tAVWL D (DATA IN) tWLQZ Q (DATA OUT) HIGH-Z HIGH-Z tDVWH DATA VALID tWHQX tWHDX tWHAX
MOTOROLA FAST SRAM
MCM6209C 5
WRITE CYCLE 2 (E Controlled, See Notes 1, 2, and 3)
- 12 Parameter Write Cycle Time Address Setup Time Address Valid to End of Write Enable to End of Write Data Valid to End of Write Data Hold Time Write Recovery Time Symbol tAVAV tAVEL tAVEH tELEH, tELWH tDVEH tEHDX tEHAX Min 12 0 10 8 6 0 0 Max -- -- -- -- -- -- -- - 15 Min 15 0 12 10 7 0 0 Max -- -- -- -- -- -- -- - 20 Min 20 0 15 12 8 0 0 Max -- -- -- -- -- -- -- - 25 Min 25 0 20 15 10 0 0 Max -- -- -- -- -- -- -- - 35 Min 35 0 20 15 10 0 0 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns 4, 5 Notes 3
NOTES: 1. A write occurs during the overlap of E low and W low. 2. For Output Enable devices, if G goes low coincident with or after W goes low, the output will remain in a high impedance state. 3. All timings are referenced from the last valid address to the first transitioning address. 4. If E goes low coincident with or after W goes low, the output will remain in a high impedance state. 5. If E goes high coincident with or before W goes high, the output will remain in a high impedance state.
WRITE CYCLE 2 (E Controlled, See Note 2)
tAVAV A (ADDRESS) tAVEH E (CHIP ENABLE) tAVEL tWLEH W (WRITE ENABLE) tDVEH D (DATA IN) DATA VALID tEHDX tELEH tELWH tEHAX
Q (DATA OUT)
HIGH-Z
ORDERING INFORMATION
(Order by Full Part Number) MCM
Motorola Memory Prefix Part Number
6209C X
XX
XX
Shipping Method (R2 = Tape and Reel, Blank = Rails) Speed (15 = 15 ns, 20 = 20 ns, 25 = 25 ns, 35 = 35 ns) Package (P = Plastic DIP, J = Plastic SOJ)
Full Part Numbers -- MCM6209CP15 MCM6209CP20 MCM6209CP25 MCM6209CP35
MCM6209CJ15 MCM6209CJ20 MCM6209CJ25 MCM6209CJ35
MCM6209CJ15R2 MCM6209CJ20R2 MCM6209CJ25R2 MCM6209CJ35R2
MCM6209C 6
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
P PACKAGE 300 MIL PLASTIC CASE 710B-01 -ANOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION A AND B DOES NOT INCLUDE MOLD FLASH. MAXIMUM MOLD FLASH 0.25 (0.010). DIM A B C D E F G J K L M N S MILLIMETERS MIN MAX 34.55 34.79 7.62 7.12 4.57 3.81 0.53 0.39 1.27 BSC 1.39 1.15 2.54 BSC 0.30 0.21 3.42 3.18 7.62 BSC 0 15 0.51 1.01 INCHES MIN MAX 1.360 1.370 0.280 0.300 0.150 0.180 0.015 0.021 0.050 BSC 0.045 0.055 0.100 BSC 0.008 0.012 0.125 0.135 0.300 BSC 0 15 0.020 0.040
28 1
15
-B14
L C
-TSEATING PLANE
K E F D 28 PL 0.25 (0.010)
M
N G J 28 PL M
S
TA
0.25 (0.010)
M
TB
J PACKAGE 300 MIL SOJ CASE 810B-03
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. DIMENSION A & B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 3. CONTROLLING DIMENSION: INCH. 4. DIM R TO BE DETERMINED AT DATUM -T-. 5. 810B-01 AND -02 OBSOLETE, NEW STANDARD 810B-03. S MILLIMETERS MIN MAX 18.29 18.54 7.74 7.50 3.75 3.26 0.50 0.39 2.48 2.24 0.81 0.67 1.27 BSC 0.50 -- 1.14 0.89 0.64 BSC 0 10 1.14 0.76 8.64 8.38 6.86 6.60 1.01 0.77 INCHES MIN MAX 0.720 0.730 0.295 0.305 0.128 0.148 0.015 0.020 0.088 0.098 0.026 0.032 0.050 BSC 0.020 -- 0.035 0.045 0.025 BSC 0 10 0.030 0.045 0.330 0.340 0.260 0.270 0.030 0.040
F DETAIL Z
28 15
N D 24 PL 0.18 (0.007)
M
1 14
TA
S
-AL G M
H BRK
0.18 (0.007) P -BM
TB
S
E 0.10 (0.004) K DETAIL Z -TSEATING PLANE
C
R 0.25 (0.010)
S
S RAD TB
S
DIM A B C D E F G H K L M N P R S
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MOTOROLA FAST SRAM
MCM6209C 7
Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
MCM6209C 8
CODELINE TO BE PLACED HERE
*MCM6209C/D*
MCM6209C/D MOTOROLA FAST SRAM

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